Integration of semiconductors has been conventional and is presently implemented by a silicon process and its role is clearly separated from packaging technology. For example, it is the silicon process that has mainly implemented integrating semiconductors, adding functions and creating values. Expenses of developing and fabricating an integrated circuit process, however, have kept on increasing; for example, the expenses of developing a 65 mm node have reached to 9 billion dollars all over the world, so that only few manufacturers can afford to cover them. As a result, a trend of monopolizing the few manufacturers is driving.
Moore's Law shows miniaturizing a silicon process which has resulted in reducing one silicon technology node (a 30% miniaturization e.g., the integration in which a cell size becomes half of the original size and chip integration becomes double) into 1.7 tenth in the past decade by updating the same process every two years while the packaging technology has resulted in reducing a wire radius from 100 μm to 30 μm pitches, flip-chip connection from 250 μm to 150 μm pitches, and a wiring board technology has resulted in reducing a 75 μm width to 25 μm, with more or less three tenth of the initial size, having a different reducing speed. A degree of reducing speed is estimated to further differentiate depending on these technologies as a future trend.
Although small integration technology is available and found in SIP and POP, it is extremely difficult even for the conventional packaging technology to implement high density integration with several times more than the present density to be an extension on its technology. Furthermore, chip integration in the final products is, presently limited by packaging and mounting technologies. The present time likely desires large-scale integration other than a silicon process, and breakthrough of miniaturizing mounting wire connections capable of realizing higher informatization technology, implementation of portability, downsizing and lower costs.
Technologies available in the conventional SIP, POP and the three-dimensional chip module are featured in the following documents.
As a first example of the conventional technology, it is known that the structure includes a thin wiring film with chips connected and an adhesive film alternatively laminated and formed via-holes connected to both films (refer to FIG. 4 in Patent Document 1).
As a second example of the conventional technology, it discloses a structure wherein semiconductor chips are loaded on the Paper Thin Package (PTP) substrate equipped with a via-connection electrode; the semiconductor chips are coupled to a core substrate equipped with a via-connection electrode superposed, and they are laminated by hot pressing (refer to FIG. 5 in Patent Document 2).
As a third example of the conventional technology, it discloses a structure wherein a plurality of the substrates equipped with conducting circuits and inter-layer conducting units are prepared; IC chips are loaded into the holes formed on the substrates, and these are superposed, pressed and laminated (refer to FIGS. 6, 9, and 12 in Patent Document 3).
As a fourth example of the conventional technology, it is known as a structure in which through-holes are drilled on a plurality of the chips and conducting resins are embedded in them, then connected for lamination (refer to FIG. 1 in Patent Document 1).
It is further known as a method for laminating plural chips by means of forming bumps above and below the through-holes of electrodes drilled on the chips, and coupling the bumps, or as a structure wherein one layer of plural Wafer Level Packages (WLPs) is embedded into the circuit board to increase a module mounting density.    Patent Document 1 Japanese Unexamined Patent Application, Publication No. H09-232503    Patent Document 2 Japanese Unexamined Patent Application, Publication No. 2002-343934    Patent Document 3 Japanese Unexamined Patent Application, Publication No. 2003-303938    Patent Document 4 Japanese Patent No. 2871636
The conventional technology has features, limitations and problems that can be summarized as follows:
(1) Problems in Using Bare Chips
A probe test is implemented to bare chips on the wafer, and these bare chips are merely loaded onto a substrate as a laminate structure that is mainly used in the laminate structure of the conventional technology. Owing to demands on down-sizing and thin models, bare chips are prone to be thinner; as well as groups of the terminals formed in the bare chips that are also prone to have narrow pitches. Although electric characteristics tests for wafer level and burn-in test technology have remarkably developed in recent years, they are still imperfect in comparison with those adapted to unfinished products (package products). For example, a prober in a semiconductor inspection device has a difficulty in measuring high frequency of a few 100 MHz or higher under mass production because of the length, the minor diameter and the small pitch of its inspection needle are limited. It also has a sorting capability problem for non-defective products with electric characteristics of the bare chips; and an inspection limitation caused by costs; including a higher prober that also supports a multi-pin test of more than one thousand pins which are available in logic products. Furthermore, removing initial defects by a burn-in test is also limited.
In cases where large integration is implemented with unfinished products under such electric characteristics and reliability, a cost problem will largely occur in a yield of the integrated products and expenses of the final test will also incur. It is the biggest problem in the current SIP, and a multi-chip module of which integration density is limited.
Although high integration requires an integrated circuit chip with an ultrathin thickness (which is further reduced from a thickness of 100 μm or less to 10 μm or less), several problems occur such as distortion, deviation, splits and cracks to the bare chip itself caused by insufficient mechanical intensity applied to the integrated circuit chip, uneven stress on both surfaces, and a quality deterioration of the chip occurs at the time of fabricating and handling with problems of weak humidity resistance and weak chemical resistance of an exposed bare die.
(2) Problems in Using the Packaged. Products as a Component
In cases where packaged products are used as components, a problem of a bare chip test can be solved by means of implementing a final test to an element in a package and using the element for integration. However, another problem is left in the thickness (a few 10 μm or more) of an interposer (circuit board) itself, and the limitation of miniaturizing wire connections on an interposer of the chip, resulting in defects for down-sizing, thinner-modeling and higher integration (refer to (3) below). The bare chip itself has a limitation of ultrathin-modeling as described above, and the packaged products are further packaged, so dual costs incur as a problem. Although an example is known where a structure includes the packaged products embedded in the circuit board, it is difficult to make a wiring between the embedded packaged products because the packaged products can only be embedded in one layer of the substrate. The example has a problem of less competition in comparison with other existing technology (System in Package; SiP), considering its wiring costs.
(3) Limitation of Wiring Connection Technology, Wire Bond, and Bump
A wire bond can only have a wire radius of 15 μm or longer; due mainly to the limitation of a capillary; a joint pad also has a difficulty in implementing with 25 μm or less. Since wiring is basically connected between the upper and lower chips, and between the chip and the interpose; it is difficult to implement large integration (with 10 layers or more).
Forming a bump is costly, thus it is difficult to provide a 20 μm pitch, and a radius of 10 μm or less.
In cases of a stacked structure, a problem arises in limiting a large three-dimensional integration because 1) wiring is basically laminated between the upper and lower chips, and connected between the chip and the interposer, 2) it is therefore necessary for the wired bare chips to be processed, resulting in complicated wiring, 3) it is difficult to directly connect wiring even in the horizontal direction without an in-process circuit board.
(4) The limitation of technology that aligns bare chips in or above circuit boards and laminates the circuit boards with adhesion or thermal compression
As previously mentioned, bare chip integration has basic problems. Therefore, it is not appropriate to apply stacking separate substrates with the bare chips mounted and bonding them with adhesion for small and thin-sized integrated modules; limiting its application field because micro patterns are limited owing to stacking accuracy, distortion and deviation of the substrates, and thermal compression occurs stress damage to particularly thin bare chips.
(5) Where chip lamination is implemented by means of drilling through-holes in the bare chips, embedding these holes with conducting resins and adhering upper and lower chips, it is possible to implement high integration with smaller shapes, but the high integration is limited because the bare chips have a basic problem, as well as problems of reducing yield caused by drilling the through-holes in the bare chips, quality deterioration, and higher costs, and further problems arise in positioning accuracy by adhesion, the adhesion reliability. Where bumps are formed above and under the through-hole electrodes and chip lamination is implemented by bump connection, reliability of multilayer bumps and fabricating costs become problems. Where lamination is basically implemented via through-holes in the chips, a problem arises in incurring costs for separately preparing additional circuits to the chips in order to secure selectivity because wiring is so limited that no chip selectivity can be secured. In the limited wiring function, integration improvement of the module is limited. As a result, fabricating exclusive chips drastically increases costs.
(6) The conventional technology has not provided consistent uniformed structure and fabricating methods including future miniaturization and integration possibilities because of various structures and fabricating methods from a view point of meeting a short-term requirement of applications, including integrated circuit chips. Therefore, more amounts of time are consumed in setting technical goals, processes of development and mass production, development of material jigs and tools, standardization and improvement causing slower development speed and higher costs as a problem as well.
Under the above-mentioned background, it summarizes the current state that no method is provided using any interposers that implement ultra integration of the integrated circuit chips, assuring Known Good Die (KGD), which provides electric characteristics and reliability equal to the complete products, aligning in the third dimension a basic element structure capable of supporting ultrathin bare chips (with thickness from 200 μm or less to a few μm) and its basic elements with high density wiring, and capable of basically maintaining the same structure and the fabricating method to the future advance of the technical ultrathin-modeling and miniaturization.